View AD5122_7320099.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dual channel, 128- /256 - position, spi, nonvolatile digital potentiometer data sheet AD5122 / ad5142 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is g ranted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 analog devices, inc. all rights reserved. technical support www.analog.com features 10 k and 100 k resistance options resistor tolerance: 8% maximum wiper current: 6 ma low temperature coefficient: 35 ppm/c wide bandwidth: 3 mhz fast start - up time < 75 s linear gain setting mode single - and dual - supply operation indepen dent logic supply : 1.8 v to 5.5 v wide operating temperature : ? 40 c to +125c 3 mm 3 mm package option 4 kv esd protection applications portable electronics level adjustment lcd panel brightness and contrast controls programmable filters, delays, and ti me constants programmable power supplies functional block dia gram v dd inde p v ss gnd v logic 7/8 serial interface power-on reset rdac1 input register 1 rdac2 input register 2 eeprom memory a1 w1 b1 a2 w2 b2 AD5122/ ad5142 sync sclk sdi sdo reset 10880-001 figure 1. general description the AD5122 / ad5142 potentiometers provides a nonvolatile solution for 128 - /256 - position adjustment applications , offering guaranteed low resistor tolerance errors of 8% and up to 6 ma current density in the a x , b x , and w x pins. the low resistor tolerance and low nominal temperature coefficient s implify open - loop applications as well as applications requiring tolerance matching. the linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminals, through the r aw and r wb string resistors , allow i ng very accurate resistor matching. the high bandwidth and low total harmonic distortion (thd) ensure optimal performance for ac signals, making these devices suitable for filter design. the low wiper resistance of only 40 ? at the ends of the resistor array allow s for pin - to - pin connection. the wiper values can be set through an spi - compatible digital interface that is also used to read back the wiper register and ee prom content s. the AD5122 / ad5142 is available in a compact , 16- lead, 3 mm 3 mm lfcsp and a 16 - lea d tssop. the parts are guaranteed to operate over the extended industrial temperature range of ? 40c to +125c. table 1 . family models model channel position interface package ad5123 1 quad 128 i 2 c lfcsp ad5124 quad 128 spi/i 2 c lfcsp ad5124 quad 128 spi tssop ad5143 1 quad 256 i 2 c lfcsp ad5144 quad 256 spi/i 2 c lfcsp ad5144 quad 256 spi tssop ad5144a quad 256 i 2 c tssop AD5122 dual 128 spi lfcsp/tssop AD5122a dual 128 i 2 c lfcsp/tssop ad5142 dual 256 spi lfcsp/tssop ad5142a dual 256 i 2 c lfcsp/tssop ad5121 si ngle 128 spi/i 2 c lfcsp ad5141 single 256 spi/i 2 c lfcsp 1 two potentiometers and two rheostats. free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics AD5122 .......................................... 3 electrical characteristics ad5142 .......................................... 6 interface timing specifications .................................................. 9 shift register and timing diagrams ....................................... 10 absolute maximum ratings .......................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configurations and function descriptions ......................... 12 typical performance characteristics ........................................... 14 test circuits ..................................................................................... 19 theory of operation ...................................................................... 20 rdac register and eeprom .................................................. 20 input shift register .................................................................... 20 spi serial data interface ............................................................ 20 advanced control modes ......................................................... 23 eeprom or rdac register protection ................................. 24 indep pin ................................................................................... 24 rdac architecture .................................................................... 27 programming the variable resistor ......................................... 27 programming the potentiometer divider ............................... 28 terminal v oltage operating range ......................................... 28 power - up sequence ................................................................... 28 layout and power supply biasing ............................................ 28 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 30 revision history 10/ 12 rev ision 0: initial version free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 3 of 32 specifications electrical character istics ad512 2 v dd = 2.3 v to 5.5 v, v ss = 0 v; v dd = 2.25 v to 2.75 v, v ss = ?2.25 v to ?2.75 v; v logic = 1.8 v to 5.5 v, ?40c < t a < +125c, unless otherwise noted. table 2 . parameter symbol test conditions/comments min typ 1 max unit dc characteristics rheostat mode (all rdacs) resolution n 7 bits resistor integral nonlinearity 2 r - inl r ab = 10 k ? v dd 2.7 v ? 1 0. 1 + 1 lsb v dd < 2.7 v ? 2.5 1 + 2.5 lsb r ab = 100 k ? v dd 2.7 v ? 0.5 0.1 + 0.5 lsb v dd < 2.7 v ? 1 0. 25 + 1 lsb resistor differential nonlinearity 2 r - dnl ? 0.5 0. 1 +0.5 lsb nominal resistor tolerance r ab /r ab ? 8 1 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 code = full scale 35 ppm/c wiper resistance 3 r w code = zero scale r ab = 10 k ? 55 125 ? r ab = 100 k ? 130 400 ? bottom s cale or top scale r bs or r ts r ab = 10 k ? 40 80 ? r ab = 100 k ? 60 230 ? nominal resistance match r ab1 /r ab2 code = 0xff ? 1 0.2 +1 % dc characteristics potentiometer divider mode (all rdacs) integral nonlinearity 4 inl r ab = 10 k ? ? 0.5 0. 1 + 0.5 lsb r ab = 100 k ? ? 0. 25 0.1 +0. 25 l sb differential nonlinearity 4 dnl ? 0. 25 0. 1 +0. 25 lsb full - scale error v wfse r ab = 10 k ? ? 1 .5 ? 0.1 lsb r ab = 100 k ? ? 0.5 0. 1 + 0.5 lsb zero - scale error v wzse r ab = 10 k ? 1 1.5 lsb r ab = 100 k ? 0. 25 0.5 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 5 ppm/c free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 4 of 32 parameter symbol test conditions/comments min typ 1 max unit resistor terminals maximum continuous current i a , i b , and i w r ab = 10 k ? ? 6 +6 ma r ab = 100 k ? ? 1.5 +1.5 ma terminal voltage range 5 v ss v dd v capacitance a, capacitance b 3 c a , c b f = 1 mhz, measured to gnd , code = half scale r ab = 10 k ? 25 pf r ab = 100 k ? 12 pf capacitance w 3 c w f = 1 mhz, measured to gnd, code = half scale r ab = 10 k ? 12 pf r ab = 100 k ? 5 pf common - mode leakage current 3 v a = v w = v b ? 500 15 + 500 na digital inputs input logic 3 high v inh v logic = 1.8 v to 2.3 v 0.8 v logic v v logic = 2.3 v to 5.5 v 0.7 v logic v low v inl 0.2 v logic v input hysteresis 3 v hyst 0.1 v logic v input current 3 i in 1 a input capacitance 3 c in 5 pf digital outputs output high voltage 3 v oh r pull - up = 2.2 k ? to v logic v logic v output low voltage 3 v ol i sink = 3 ma 0.4 v i sink = 6 ma , v logic > 2.3 v 0.6 v three - state leakage current ? 1 +1 a three - state output capacitance 2 pf power supplies single - supply power range v ss = gnd 2.3 5.5 v dual - supply power range 2.25 2.75 v logic supply range single s upply, v ss = gnd 1.8 v dd v dual s upply, v ss < gnd 2.25 v dd v positive supply current i dd v ih = v logic or v il = gnd v dd = 5.5 v 0.7 5.5 a v dd = 2.3 v 400 na negative supply current i ss v ih = v logic or v il = gnd ? 5.5 ? 0.7 a eeprom store current 3 , 6 i dd_ eeprom _store v ih = v logic or v il = gnd 2 ma eeprom read current 3 , 7 i dd_ eeprom _read v ih = v logic or v il = gnd 320 a logic supply current i logic v ih = v logic or v il = gnd 1 120 na power dissipation 8 p diss v ih = v logic or v il = gnd 3.5 w power supply rejection ratio psr r ? v dd / ? v ss = v dd 10%, code = full scale ? 66 ? 60 db free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 5 of 32 parameter symbol test conditions/comments min typ 1 max unit dynamic characteristics 9 bandw idth bw ? 3 db r ab = 10 k ? 3 mhz r ab = 100 k ? 0.43 mhz total harmonic distortion thd v dd /v ss = 2.5 v, v a = 1 v rms, v b = 0 v, f = 1 khz r ab = 10 k ? ? 80 db r ab = 100 k ? ? 90 db resistor noise density e n_wb code = half scale, t a = 25c, f = 10 khz r ab = 10 k ? 7 nv/hz r ab = 100 k ? 20 nv/hz v w settling time t s v a = 5 v, v b = 0 v, from zero scale to full scale, 0.5 lsb error band r ab = 10 k ? 2 s r ab = 100 k ? 12 s crosstalk (c w1 /c w2 ) c t r ab = 10 k ? 10 nv - sec r ab = 100 k ? 25 nv - sec analog crosstalk c ta ? 90 db endurance 10 t a = 25c 1 mcycles 100 kcycles data retention 11 50 years 1 typical values represent average readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v . 2 resistor i ntegral nonlinearity (r - inl ) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. the maximum wiper current is limited to (0 .7 v dd )/r ab . 3 guaranteed by design and characterization, not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limi ts of 1 lsb maximum are guaranteed monotonic operating conditions. 5 r esistor t erminal a, r esistor t erminal b, and r esistor t erminal w have no limitations on polarity with respect to each other. dual - supply operation enables ground referenced bipolar sign al adjustment . 6 different from operating current; supply current for eeprom program lasts approximately 30 ms . 7 different from operating current; supply current for eeprom read lasts approximately 20 s . 8 p diss is calculated from (i dd v dd ) + (i logic v logic ). 9 all dynamic characteristics use v dd / v ss = 2.5 v, and v logic = 2. 5 v. 10 endurance is qualified to 100,000 cycles per jedec standard 22, method a117 and measured at ?40c to +125c . 11 retention lifetime equivalent at junction temperature (t j ) = 125c per jedec standard 22, method a117. retention lifetime , based on an activation ener gy of 1 ev , derates with junction temperature in the flash/ee memory. free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 6 of 32 electrical character istics ad514 2 v dd = 2.3 v to 5.5 v, v ss = 0 v; v dd = 2.25 v to 2.75 v, v ss = ?2.25 v to ?2.75 v; v logic = 1.8 v to 5.5 v, ?40c < t a < +125c, unless otherwise noted. table 3 . parameter symbol test conditions/comments min typ 1 max unit dc charact eristics rheostat mode (all rdacs) resolution n 8 bits resistor integral nonlinearity 2 r - inl r ab = 10 k ? v dd 2.7 v ? 2 0.2 +2 lsb v dd < 2.7 v ? 5 1.5 +5 lsb r ab = 100 k ? v dd 2.7 v ? 1 0.1 +1 lsb v dd < 2.7 v ? 2 0.5 +2 lsb resistor differential nonlinearity 2 r - dnl ? 0.5 0.2 +0.5 lsb nominal resistor tolerance r ab /r ab ? 8 1 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 code = full scale 35 ppm/c wiper resistance 3 r w code = zero scale r ab = 10 k ? 55 125 ? r ab = 100 k ? 130 400 ? bottom s cale or top scale r bs or r ts r ab = 10 k ? 40 80 ? r ab = 100 k ? 60 230 ? nominal resistance match r a b1 /r ab2 code = 0xff ? 1 0.2 +1 % dc characteristics potentiometer divider mode (all rdacs) integral nonlinearity 4 inl r ab = 10 k ? ? 1 0.2 +1 lsb r ab = 100 k ? ? 0.5 0.1 +0.5 lsb differential nonlinearity 4 dnl ? 0.5 0.2 +0.5 lsb full - scale error v wfse r ab = 10 k ? ? 2.5 ? 0.1 lsb r ab = 100 k ? ? 1 0.2 +1 lsb zero - scale error v wzse r ab = 10 k ? 1.2 3 lsb r ab = 100 k ? 0.5 1 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 5 ppm/c free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 7 of 32 parameter symbol test conditions/comments min typ 1 max unit resistor terminals maximum continuous current i a , i b , and i w r ab = 10 k ? ? 6 +6 ma r ab = 100 k ? ? 1.5 +1.5 ma terminal voltage range 5 v ss v dd v capacitance a, capacitance b 3 c a , c b f = 1 mhz, measured to gnd , code = half scale r ab = 10 k ? 25 pf r ab = 100 k ? 12 pf capacitance w 3 c w f = 1 mh z, measured to gnd, code = half scale r ab = 10 k ? 12 pf r ab = 100 k ? 5 pf common - mode leakage current 3 v a = v w = v b ? 500 15 + 500 na digital inputs input logic 3 high v inh v logic = 1.8 v to 2.3 v 0.8 v logic v v logic = 2.3 v to 5.5 v 0.7 v logic v low v inl 0.2 v logic v input hysteresis 3 v hyst 0.1 v logic v input current 3 i in 1 a input capacitance 3 c in 5 pf digital outputs output high voltage 3 v oh r pull - up = 2.2 k ? to v logic v logic v output low voltage 3 v ol i sink = 3 ma 0.4 v i sink = 6 ma , v logic > 2.3 v 0.6 v three - state leakage current ? 1 +1 a three - state output capacitance 2 pf power supplies single - supply power range v ss = gnd 2.3 5.5 v dual - supply power range 2.25 2.75 v logic supply range single s upply, v ss = gnd 1.8 v dd v dual s upply, v ss < gnd 2.25 v dd v positive supply current i dd v ih = v logic or v il = gnd v d d = 5.5 v 0.7 5.5 a v dd = 2.3 v 400 na negative supply current i ss v ih = v logic or v il = gnd ? 5.5 ? 0.7 a eeprom store current 3 , 6 i dd_ eeprom _store v ih = v logic or v il = gnd 2 ma eeprom read current 3 , 7 i dd_ eeprom _read v ih = v logic or v il = gnd 320 a logic supply current i logic v ih = v logic or v il = gnd 1 120 na power dissipation 8 p diss v ih = v logic or v il = gnd 3.5 w power supply rejection ratio psr r ? v dd / ? v ss = v dd 10%, code = full scale ? 66 ? 60 db free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 8 of 32 parameter symbol test conditions/comments min typ 1 max unit dynamic characteristics 9 bandw idth bw ? 3 db r ab = 10 k ? 3 mhz r ab = 100 k ? 0.43 mhz total harmonic distortion thd v dd /v ss = 2.5 v, v a = 1 v rms, v b = 0 v, f = 1 khz r ab = 10 k ? ? 80 db r ab = 100 k ? ? 90 db resistor noise density e n_wb code = half scale, t a = 25c, f = 10 khz r ab = 10 k ? 7 nv/hz r ab = 100 k ? 20 nv/hz v w settling time t s v a = 5 v, v b = 0 v, from zero scale to full scale, 0.5 lsb error band r ab = 10 k ? 2 s r ab = 100 k ? 12 s crosstalk (c w1 /c w2 ) c t r ab = 10 k ? 10 nv - sec r ab = 100 k ? 25 nv - sec analog crosstalk c ta ? 90 db endurance 10 t a = 25c 1 mcycles 100 kcycles data retention 11 50 years 1 typical values represent average readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v . 2 resistor i ntegral nonlinearity (r - inl) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. the m aximum wiper current is limited to (0.7 v dd )/r ab . 3 guaranteed by design and characterization, not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 r esistor t erminal a, r esistor t erminal b, and r esistor t erminal w have no limitations on polarity with respect to each other. dual - supply operation e nables ground referenced bipolar signal adjustment . 6 different from operating current; supply current for eeprom program lasts approximately 30 ms . 7 different from operating current; supply current for eeprom read lasts approximately 20 s . 8 p diss is ca lculated from (i dd v dd ) + (i logic v logic ). 9 all dynamic characteristics use v dd / v ss = 2.5 v, and v logic = 2. 5 v. 10 endurance is qualified to 100,000 cycles per jedec standard 22, method a117 and measured at ?40c to +125c . 11 retention lifetime equi valent at junction temperature (t j ) = 125c per jedec standard 22, method a117. retention lifetime , based on an activation ener gy of 1 ev , derates with junction temperature in the flash/ee memory. free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 9 of 32 interface timing specification s v logic = 1.8 v to 5.5 v; all specifications t min to t max , unless otherwise noted . table 4 . spi interface parameter 1 test conditions/comments min typ max unit description t 1 v logic > 1.8 v 20 ns sclk cycle time v logic = 1.8 v 30 ns t 2 v logic > 1.8 v 10 ns sclk high tim e v logic = 1.8 v 15 ns t 3 v logic > 1.8 v 10 ns sclk low time v logic = 1.8 v 15 ns t 4 10 ns sync -to - sclk falling edge setup time t 5 5 ns data setup time t 6 5 ns data hold time t 7 10 ns sync rising edge to next sclk fall ignored t 8 2 20 ns minimum sync high time t 9 3 50 ns sclk rising edge to sdo valid t 10 500 ns sync rising edge to sdo pin disable 1 all input signals are specified with t r = t f = 1 ns/v (1 0% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 2 refer to t eeprom_program and t eeprom_readback for memory commands operations (see table 5 ) . 3 r pull_up = 2.2 k ? to v dd with a capacitance load of 168 pf. table 5 . control pins parameter min typ max unit description t 1 0.1 10 s reset low time t eeprom_program 1 15 50 ms memory program time (not shown in figure 5 ) t eeprom_readback 7 30 s memory readback time (not shown in figure 5 ) t power_up 2 75 s start - up time (not shown in figure 5 ) t reset 30 s reset eeprom restore time (not shown in figure 5 ) 1 eep rom program time depends on the temperature and eeprom write cycles. higher timing is expected at lower temperature s and higher write cycles. 2 maximum time after v dd ? v ss is equal to 2.3 v. free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 10 of 32 shi f t r egister and timing d iagrams data bits db8 db15 (msb) db0 (lsb) d7 d6 d5 d4 d3 d2 d1 d0 address bits a0 a1 a2 c2 c1 c0 a3 c3 control bits db7 10880-002 figure 2 . input shift register content s c3 t 4 t 2 t 3 t 5 t 6 c2 c1 c0 d7 d6 d5 d2 d1 d0 sdi *previous command received. sclk sync c3* sdo c2* c1* c0* d7* d6* d5* d2* d1* d0* t 8 t 9 t 10 t 7 t 1 10880-003 figure 3. spi serial interface timing diagram, cpol = 0, cpha = 1 c3 t 4 t 2 t 3 t 5 t 6 c2 c1 c0 d7 d6 d5 d2 d1 d0 sdi *previous command received. sclk sync c3* sdo c2* c1* c0* d7* d6* d5* d2* d1* d0* t 8 t 9 t 10 t 7 t 1 10880-004 figure 4. spi serial int erface timing diagram, cpol = 1, cpha = 0 sclk sync reset t 1 10880-005 figure 5 . control pins timing diagram free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 11 of 32 absolute maximum rat ings t a = 25c, unless otherwise noted. table 6 . parameter rating v dd to gnd ? 0.3 v to +7.0 v v ss t o gnd + 0.3 v to ? 7.0 v v dd to v ss 7 v v logic to gnd ? 0.3 v to v dd + 0.3 v or +7.0 v (whichever is less) v a , v w , v b to gnd v ss ? 0.3 v, v dd + 0.3 v or +7.0 v (whichever is less) i a , i w , i b pulsed 1 frequency > 10 khz r aw = 10 k? 6 ma/d 2 r aw = 100 k? 1.5 ma/d 2 frequency 10 khz r aw = 10 k? 6 ma/d 2 r aw = 100 k? 1.5 ma/d 2 digital inputs ? 0.3 v to v logic + 0.3 v or +7 v (whichever is less) operating temperature range, t a 3 ? 40 c to +125c maximum junction temperature, t j m ax imum 150c storage temperature range ? 65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec t o 40 sec package power dissipation (t j max ? t a )/ ja esd 4 4 kv ficdm 1.5 kv 1 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 d = p ulse duty factor . 3 includes programming of eeprom memory. 4 human body model (hbm) classification . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is defined by the jedec jesd51 standard, and the value is dependent on the test board and test environment. table 7 . thermal resistance package type ja jc unit 16- lead lfcsp 89.5 1 3 c/w 16- lead tssop 150.4 1 27.6 c/w 1 jedec 2s2p test board, still a i r (0 m/sec air flow). esd caution free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 12 of 32 pin configuration s and function descrip tions reset sync notes 1. internally connect the exposed pad to v ss . AD5122/ ad5142 top view (not to scale) pin 1 indic a t or 1 gnd 2 a1 3 w1 4 b1 1 1 sclk 12 sdi 10 v logic 9 v dd inde p sdo 5 v ss 6 a2 7 w2 8 b2 15 16 14 13 10880-006 figure 6. 16 - lead lfcsp pin configuration table 8 . 16 - lead lfcsp pin function descriptions pin no. mnemoni c description 1 gnd ground pin, logic ground reference. 2 a1 terminal a of rdac1. v ss v a v dd . 3 w1 wiper t erminal of rdac1. v ss v w v dd . 4 b1 terminal b of rdac1. v ss v b v dd . 5 v ss negative power supply. decouple t his pin with 0.1 f ceramic capacitors and 10 f capacitors . 6 a2 terminal a of rdac2. v ss v a v dd . 7 w2 wip er t erminal of rdac2. v ss v w v dd . 8 b2 terminal b of rdac2. v ss v b v dd . 9 v dd positive power supply. decouple t his pin with 0.1 f ceramic capacitors and 10 f capacitors . 10 v logic logic power supply; 1.8 v to v dd . decouple t his pin with 0.1 f ceramic capacitors and 10 f capacitors. 11 sclk serial clock line. data is clocked in at the logic low transition. 12 sdi serial data input . 13 sdo serial data output. this is an o pen - drain output pin, and it needs an external pull - up resistor . 14 sync synchronization input , active low. when sync returns high, data is loaded into the input shift register . 15 indep linear gain setting mode at power - up. each string resistor is loaded independently from its associat ed memory location. if indep is enabled, it cannot be disabled by software. 16 reset hardware reset pin. refresh the rdac registers from ee prom . reset is activated at the logic low. i f this pin is not used , t ie reset to v logic . epad internally co nnect the exposed pad to v ss . free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 13 of 32 1 2 3 4 5 6 7 8 inde p a1 w1 b1 reset a2 v ss gnd 16 15 14 13 12 1 1 10 9 sdo sdi sclk v logic v dd w2 b2 AD5122/ ad5142 top view (not to scale) sync 10880-007 figure 7. 16 - lead tssop , spi interface pin configuration table 9 . 16 - lead tssop , spi interface pin function description s pin no. mnemonic description 1 indep linear gain setting mode at power - up. each string resistor is loaded independently from its associate d memory location. if indep is enabled, it cannot be disabled by software. 2 reset hardware rese t pin. refresh the rdac register s from ee prom . reset is activated at the logic lo w . i f this pin is not used , t ie reset to v logic . 3 gnd ground pin, logic ground reference. 4 a1 terminal a of rdac1 . v ss v a v dd . 5 w1 wiper t erminal of rdac1. v ss v w v dd . 6 b1 terminal b of rdac1 . v ss v b v dd . 7 v ss negative power supply. decouple t his pin with 0.1 f ceramic capacitors and 10 f capacitors . 8 a2 terminal a of rdac2 . v ss v a v dd . 9 w2 wipe r t erminal of rdac2. v ss v w v dd . 10 b2 terminal b of rdac2 . v ss v b v dd . 11 v dd positive power supply. decouple t his pin with 0.1 f ceramic capacitors and 10 f capacitors . 12 v logic logic power supply; 1.8 v to v dd . decouple t his pin with 0.1 f ceramic capacitors and 10 f capacitors . 13 sclk serial clock line. data is clocked in at the logic low transition . 14 sdi serial data input . 15 sdo serial data output. this is an o pen - drain output pin, and it needs an external pull - up resistor . 16 sync synchronization input , active low. when sync returns high, data is loaded into the input shift register . free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 14 of 32 typical performance characteristics ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 100 200 r-inl (lsb) code (decimal) 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10880-008 figure 8. r - inl vs. code ( ad5142 ) r-inl (lsb) code (decimal) ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 50 100 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10880-009 figure 9. r - inl vs. code ( AD5122 ) 0 100 200 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 in l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, + 2 5 c 10k ?, + 12 5 c 100k ?, ?4 0 c 100k ?, + 2 5 c 100k ?, + 12 5 c 10880-010 figure 10 . inl vs. code ( ad5142 ) ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0 100 200 r-dn l (lsb) code (decimal) 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10880-0 1 1 figure 11 . r - dnl vs. code ( ad5142 ) code (decimal) ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0 50 100 r-dn l (lsb) 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10880-012 figure 12 . r - dnl vs. code ( AD5122 ) ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 dn l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, +2 5 c 10k ?, +12 5 c 100k ?, ?4 0 c 100k ?, +2 5 c 100k ?, +12 5 c 10880-013 0 100 200 figure 13 . dnl vs. code ( ad5142 ) free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 15 of 32 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0 50 100 in l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, + 2 5 c 10k ?, + 12 5 c 100k ?, ?4 0 c 100k ?, + 2 5 c 100k ?, + 12 5 c 10880-014 figure 14 . inl vs. code ( AD5122 ) ?50 0 50 100 150 200 250 300 350 400 450 potentiometer mode temperature coefficient (ppm/c) code (decimal) 100k ? 10k ? 10880-015 0 5 0 10 0 15 0 20 0 25 5 0 2 5 5 0 7 5 10 0 12 7 ad 512 2 ad 514 2 figure 15 . potentiometer mode temp erature c o effic ient (( v w /v w )/ t 10 6 ) vs. code 0 10 0 20 0 30 0 40 0 50 0 60 0 70 0 80 0 curr e n t ( n a ) t emper a t ur e ( c ) i d d , v dd = 2 . 3 v i d d , v dd = 3 . 3 v i d d , v dd = 5 v i l ogi c , v logic = 2 . 3 v i l ogi c , v logic = 3 . 3 v i l ogi c , v logic = 5 v v d d = v l ogi c v s s = g n d 10880-016 ?4 0 1 0 6 0 1 25 1 10 figure 16 . supply current vs. temperature ?0.14 ?0.12 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0 50 100 dn l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, +2 5 c 10k ?, +12 5 c 100k ?, ?4 0 c 100k ?, +2 5 c 100k ?, +12 5 c 10880-017 figure 17 . dnl vs. code ( AD5122 ) ?50 0 50 100 150 200 250 300 350 400 450 rhe o s t a t m o d e t empe rat ure c o e ff i c i e n t ( pp m / c ) 10k? 100k? 10880-018 code (decimal) 0 5 0 10 0 15 0 20 0 25 5 0 2 5 5 0 7 5 10 0 12 7 ad 512 2 ad 514 2 figure 18 . rheostat mode temperature coefficient (( r wb /r wb )/ t 10 6 ) vs. code 0 20 0 40 0 60 0 80 0 100 0 120 0 0 1 2 3 4 5 i l ogi c curr e n t ( a ) i n pu t vo lta g e (v) v logic = 1 . 8 v v logic = 2 . 3 v v logic = 3 . 3 v v logic = 5 v v logic = 5 . 5 v 108 80 - 0 19 figure 19 . i logic current vs. digital input voltage free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 16 of 32 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m gain (db) frequenc y (hz) ad5142 (AD5122) 0x80 (0x40) 0x40 (0x20) 0x20 (0x10) 0x10 (0x08) 0x8 (0x04) 0x4 (0x02) 0x2 (0x01) 0x1 (0x00) 0x00 10880-020 figure 20 . 10 k? gain vs. frequency vs. code ?100 ?90 ?80 ?70 ?60 ?50 ?40 20 200 2k 20k 200k thd + n (db) frequenc y (hz) 10k ? 100k ? 10880-021 v dd /v ss = 2.5v v a = 1v rms v b = gnd code = half scale noise filter = 22khz figure 21 . total harmonic distortion plus noise (thd + n) vs. frequency ?100 ?80 ?60 ?40 ?20 0 20 10 100 1k 10k 100k 1m 10m phase (degrees) frequenc y (hz) quarter scale midscale full-scale v dd /v ss = 2.5v r ab = 10k 10880-022 figure 22 . normalized phase flatness vs. frequency, r ab = 10 k? ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 gain (db) frequenc y (hz) 10 100 1k 10k 100k 1m 10m 0x80 (0x40) 0x40 (0x20) 0x20 (0x10) 0x10 (0x08) 0x8 (0x04) 0x4 (0x02) 0x2 (0x01) 0x1 (0x00) 0x00 ad5142 (AD5122) 10880-023 figure 23 . 100 k? gain vs. frequency vs. code 10k ? 100k ? ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.001 0.01 0.1 1 thd + n (db) vo lt age (v rms) v dd /v ss = 2.5v f in = 1khz code = half scale noise filter = 22 khz 10880-024 figure 24 . total harmonic distortion plus noise (thd + n) vs. amplitude ?80 ?90 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 10 100 1k 10k 100k 1m phase (degrees) frequenc y (hz) quarter scale midscale full-scale v dd /v ss = 2.5v r ab = 100k ? 10880-025 figure 25 . normalized phase flatness vs. frequency, r ab = 100 k? free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 17 of 32 0 100 200 300 400 500 600 0 1 2 3 4 5 wiper on resis t ance ( ) volt age (v) 100k, v dd = 2.3v 100k, v dd = 2.7v 100k, v dd = 3v 100k, v dd = 3.6v 100k, v dd = 5v 100k, v dd = 5.5v 10k, v dd = 2.3v 10k, v dd = 2.7v 10k, v dd = 3v 10k, v dd = 3.6v 10k, v dd = 5v 10k, v dd = 5.5v 10880-026 figure 26 . incremental wiper on resistance v s. positive power supply ( v dd ) 0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 0 10 20 30 40 50 60 bandwidth (mhz) code (decimal) ad5142 AD5122 10k ? + 0pf 10k ? + 75pf 10k ? + 150pf 10k ? + 250pf 100k ? + 0pf 100k ? + 75pf 100k ? + 150pf 100k ? + 250pf 10880-027 figure 27 . maximum bandwidth vs. code vs. net capacitance ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 5 10 15 rel a tive vo lt age (v) time ( s) 0x80 to 0x7f 100k 0x80 to 0x7f 10k 10880-028 figure 28 . maximum transition glitch 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 0 0 . 000 5 0 . 001 0 0 . 001 5 0 . 002 0 0 . 002 5 ?40 0 ?50 0 ?60 0 ?30 0 ?20 0 ?10 0 0 10 0 20 0 30 0 40 0 50 0 60 0 cu m u l a t i ve p r o bab i l i t y p r o bab i l i t y d e n s i t y r es i s t o r dr if t ( pp m ) 10880-029 figure 29 . resistor life t ime drift 10880-030 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 1 0 10 0 1 k 10 k 100 k 1 m 10 m ps rr (d b ) f r eq u en c y (h z) v d d = 5 v 10% a c v s s = g nd , v a = 4 v, v b = g n d c o d e = mi d sca l e 10k, rdac1 100k, rdac1 figure 30 . power supply rejection ratio (psrr) vs. frequency ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0 500 1000 1500 2000 rel a tive vo lt age (v) time (ns) 10880-031 figure 31 . digital feedthrough free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 18 of 32 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m gain (db) frequenc y (hz) 10k 100k 10880-032 shutdown mode enabled figure 32 . shutdown isolation vs. frequency 0 1 2 3 4 5 6 7 0 50 100 150 200 250 0 25 50 75 100 125 AD5122 theoretica l i max (ma) ad5142 code (decimal) 10880-033 10k? 100k? figure 33 . theoretical maximum current vs. code free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 19 of 32 test circuits figure 34 to figure 38 define the test conditions used in the specifications section. a w b nc i w dut v ms nc = no connect 10880-034 figure 34 . resistor integral nonlinearity error (rheostat operation; r - inl, r - dnl) a w b dut v ms v+ v+ = v dd 1lsb = v+/2 n 10880-035 figure 35 . potentiometer divider nonlinearity error (inl, dnl) a w nc b dut i w = v dd /r nomina l v ms1 v w r w = v ms1 /i w nc = no connect 10880-036 figure 36 . wiper resistance a w b v ms v+ = v dd 10% psrr (db) = 20 log v ms v dd ( ) ~ v a v dd v ms % v dd % pss ( %/% ) = v+ 10880-037 figure 37 . power supply sensitivity and power supply rejection ratio (pss, psrr) + ? dut code = 0x00 0.1v v ss t o v dd r sw = 0.1v i sw i sw w b a = nc 10880-038 figure 38 . incremental on resistance free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 20 of 32 theory of operation the AD5122 / ad5142 digital programmable potentiometers are designed to operate as true variable resistor s for analog signals within the terminal voltage range of v ss < v term < v dd . the resistor wiper position is determined by the rdac r egister contents. the rdac register acts as a scratchpad register that allows unlimited changes of resistance settings . a secondary register (the input register ) can be used to preload the rdac register data. the rdac register can be programmed with any po sition setting using the spi interface (depending on the model). when a desirable wiper position is found, this value can be stored in the eeprom memory. thereafter, the wiper position is always restored to that position for subsequent power - up s . the stori ng of eeprom data takes approximately 1 5 ms; during this time, the device is locked and does not acknowledge any new command , preventing any changes from taking place. rdac r egister and eeprom the rdac register directly controls the position of the digital potentiometer wiper. for example, when the rdac register is loaded with 0x80 ( ad5142 , 256 taps) , the wiper is connected to half scale of the variable resistor. the rdac register is a standard logic register; the re is no restriction on the number of changes allowed . it is possible to both write to and read from the rdac register using the digital interface ( see ta ble 10) . the contents of the rdac register can be stored to the eeprom usin g c ommand 9 ( see ta ble 16) . thereafter , the rdac register always set s at that position for any future on - off - on power supply sequence. it is possible to read back data saved into the eeprom with c ommand 3 ( see ta ble 10) . alternatively, the eeprom can be writ t e n to independently using c ommand 1 1 ( see ta ble 16) . input shift register for the AD5122 / ad5142 , the input shift register is 16 bits wide, as shown in figure 2 . the 16 - bit word consists of four control bits, followed by four address bits and by eight data bits . i f the AD5122 rdac or eeprom registers are read from or written to , the lowe st data bit (bit 0) is ignored. data is loaded msb first (bit 15). the four control bits determine the function of the software command as listed in ta ble 10 and ta ble 16. spi serial data interface the AD5122 / ad5142 contain a 4 - wire , spi - compatible digital interface (s di, sync , sdo , and s clk). the write sequence begins by bringing the sync line low. the sync pin must be held low until the complete data - word is loaded from the sdi pin. data is loaded in at the s clk fa lling edge transition, as shown in figure 3 and figure 4 . when sync returns high, the serial data - word is decoded according to the instructions in ta ble 16. to minimize power consumption in the digital input buffers when the part is enable d , operate all serial interface pins close to the v logic supply rails. sync interruption in a standalone write sequence for the AD5122 / ad5142 , the sync line is kept low for 16 falling edges of sclk, and the instruction is decoded when sync is pulled high. however, if the sync line is kept low for less than 16 falling edges of sclk, the input shift register content is ignored , and the write sequence is considered invalid. sdo p in the serial data output pin (sdo) serves two purposes : to read back the contents of the control , ee prom , rdac , and input registers using command 3 (see table 10 and ta ble 16 ), and to connect the AD5122 / ad5142 to daisy - chain mode. the sdo pin contains an internal open - drain output that needs an external pull - up resistor. th e sdo pin is enabled when sync is pulled low , and t he d ata is clocked out of sdo on the rising edge of sclk , as shown in figure 3 and figure 4 . free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 21 of 32 daisy - chain connection d aisy chaining minimizes the number of port pins required from the control ling ic. as shown in figure 39, the sdo pin of one package must be tie d to the sdi pin of the next package. the clock period may need to be increase d because of the propagation delay of the line between subsequent devices. when two AD5122 / ad5142 devices are daisy chained, 32 bits of data are required. the first 16 bits assigned to u2, and the second 16 bits assigned to u1 , as shown in figure 40 . keep the sync pin low until all 32 bits are clocked into their respective serial registers. the sync pin is then pulled high to complete the operation. a t ypical connection is show n in figure 39. to prevent data from mislocking ( for example, due to noise) the part includes an internal counter, if the clock falling edges count is not a multiple of 8, the part ignores the command . a valid clock count is 16, 24, or 32. the counter resets when sync returns high . mosi ss sclk miso microcontroller sdi sdo sclk sclk r p 2.2k ? r p 2.2k ? sdi sdo u1 u2 AD5122/ ad5142 AD5122/ ad5142 sync sync dais y -chain v logic v logic 10880-039 figure 39 . daisy - chain configuration db15 sclk sync mosi 1 2 16 db0 db15 sdo_u1 32 db15 db0 db15 db0 17 18 db0 input word for u2 input word for u1 input word for u2 undefined 10880-040 figure 40 . daisy - chain diagram free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 22 of 32 ta ble 10. reduced commands operation trut h table command number control bits[db15:db12] address bits [db11:db8] 1 data bits [db7:db0] 1 c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x x x nop: do nothing. 1 0 0 0 1 0 0 0 a0 d7 d6 d5 d4 d3 d2 d1 d0 write c ontents of serial register data to rdac 2 0 0 1 0 0 0 0 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to input register 3 0 0 1 1 x 0 a1 a0 x x x x x x d1 d0 read back contents d1 d0 d ata 0 1 eepro m 1 1 rdac 9 0 1 1 1 0 0 0 a0 x x x x x x x 1 copy rdac register to eeprom 10 0 1 1 1 0 0 0 a0 x x x x x x x 0 copy eeprom into rdac 14 1 0 1 1 x x x x x x x x x x x x software reset 15 1 1 0 0 a3 0 0 a0 x x x x x x x d0 software shu tdown d0 condition 0 normal mode 1 shutdown mode 1 x = dont care. table 11. reduced address bits table a3 a 2 a 1 a 0 channel stored channel memory 1 x 1 x 1 x 1 all channels not applicable 0 0 0 0 rdac1 rdac1 0 0 0 1 rdac2 not applicable 0 0 1 0 not applicable rdac2 1 x = dont care. free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 23 of 32 advanced control mod es the AD5122 / ad514 2 digital potentiometers include a set of user programming features to address the wide number of applications for these universal adjustment devices ( see ta ble 16 and table 18 ) . key pro gramming features include the following: ? input register ? linear gain setting mode ? low wiper resistance feature ? lineal i ncre ment and decrement instructions ? 6 db increment and decrement instructions ? reset ? shutdown mode input r egister the AD5122 / ad5142 include one input register per rdac register. these registers allow preloading of the value for the associate d rdac register. the se register s can be written to using command 2 and read back from using command 3 (see ta ble 16). this feature allows a synchronous update of one or all the rdac registers at the same time. the transfer from the input register to the rdac register is done synchronously by c o mmand 8 (see ta ble 16) . if new data is loaded in to a n rdac register , th is rdac register automatically overwrite s the associate d input register. linear gain setting mode the patented architecture of the AD5122 / ad5142 allows the independent control of each string resistor, r aw , and r wb . to enable this feature, use command 16 (see ta ble 16 ) to set bit d2 of the control reg ister ( see table 18 ) . this mode of operation can control the potentiometer as two independent rheostats connected at a single point, w terminal, as oppose d to potentiometer mode where each resistor is complementary, r aw = r ab ? r w b . this feature enable s a second input and a n rdac register per channel, as shown in table 17 ; however, the actual rdac content s remain unchanged . the same operations are valid for potentiometer mode and linear gai n setting mode . if the indep pin is pulled high, t he device power s up in l inear gain setting mode and load s the values stored in the associated memory locations for each channel ( see table 17 ) . the ind ep pin and d2 bit are connected internally to a logic or gate, if any o r both are 1 , the part s cannot operate in potentiometer mode. low wiper resistance f eature the AD5122 / ad51 42 include two commands to reduce the wiper resistance between the terminals when the device s achieve full scale or zero scale. these ext ra positions are called bottom scale, bs, and top scale, ts. the resistance between t erminal a and t erminal w at top s cale is specified as r ts . s imilar ly , the bottom scale re s i stance between t erminal b and terminal w is specifi ed as r bs . the contents of the rdac registers are unchanged by entering in these positions. there are three ways to exit from top scale and bottom scale: by using command 12 or command 13 (see ta ble 16) ; by loading new data in a n rdac register, which includes increment/decrement operations ; or by entering shutdown mode, command 15 (see ta ble 16). table 12 and table 13 show the truth tables for the top scale position and the bottom scale position , respectively, when the potentiometer or linear gain setting mode is enabled. table 12. top scale truth table linear gain setting mode potentiometer m ode r aw r wb r aw r wb r ab r ab r ts r ab table 13. bottom scale truth table linear gain setting mode potentiometer m ode r aw r wb r aw r wb r ts r bs r ab r bs linear increment and decrement instructions the increment and decrement commands (command 4 and command 5 in ta ble 16 ) are useful for linear step adjustment applications. these commands simplify microcontro ller software coding by allowing the controller to send an increment or decrement command to the device. the adjustment can be individual or in a ganged potentiometer arrangement, where all wiper positions are changed at the same time. for an increment com mand, executing command 4 automatically moves the wiper to the next rdac position. this command can be executed in a single channel or multiple channels . free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 24 of 32 6 db increment and decrement instructions two programming instructions produce logarithmi c taper increment or decrement of the wiper position control by an individual potentiometer or by a ganged potentiometer arrangement where all rdac register positions are changed simultaneously . the +6 db increment is activated by command 6, and the ? 6 db decrement is activated by command 7 ( see ta ble 16) . for example, starting with the zero - scale position and executing command 6 ten times moves the wiper in 6 db steps to the full - scale position . when the wiper position is ne ar the maximum setting , the last 6 db increment instruction cause s the wiper to go to the full - scale position ( see table 14) . incr ementing the wiper position by + 6 db essentially doubles the rdac register value, whereas decrementi ng the wiper position by ? 6 db halves the register value . internally, the AD5122 / ad5142 use shift registers to shift the bits left and right to achieve a 6 db increment or decrement. these fun ctions are useful for various audio/video level adjustments, especially for white led brightness settings in which human visual responses are more sensitive to large adjustments than to small adjustments. table 14 . detailed left sh ift and right shift functions for the 6 db step increment and decrement left shift (+6 db/step) right shift ( ? 6 db/step) 0000 0000 1111 1111 0000 0001 0111 1111 0000 0010 0011 1111 0000 0100 0001 1111 0000 1000 0000 1111 0001 0000 0000 0111 0010 0000 0000 0011 0100 0000 0000 0001 1000 0000 0000 0000 1111 1111 0000 0000 reset the AD5122 / ad5142 can be reset through software by executing command 14 (see ta ble 16 ) or through hardware on the low pulse of the reset pin. the res et command loads the rdac register s with the contents of the eeprom and takes approximately 30 s. the eeprom is preloaded to midscale at the factory, and initial power - up is, accordingly, at midscale. tie reset to v logic if the reset pin is not used. shutdown mode the AD5122 / ad5142 can be placed in shutdown mode by executing the software shutdown command, command 15 (see ta ble 16) ; and by setting the lsb (d0) to 1. this feature places the rdac in a special state. the contents of the rdac register are unchanged by entering shutdown mode. however, all commands listed in ta ble 16 are supported while in shutdown mode. execute command 15 (see ta ble 16 ) and set the lsb (d0) to 0 to exit shutdown mode. table 15 . truth table for shutdown mode linear gain setting mode potentiom eter mode a2 aw wb aw wb 0 n/a 1 open open r bs 1 open n/a 1 n/a 1 n/a 1 1 n/a = not applicable. ee prom or rdac register protection the eeprom and rdac registers can be protected by disabling any update to th e se registers . this can be done by using software or by using hardware. if the se registers are protect ed by software, set bit d0 and/or bit d1 ( see table 18 ) , which protect s the eeprom and rdac registers independently . when rdac is protected, the only operation a llowed is to copy the eeprom into the rdac register . indep p in if the indep pin is pulled high at power - up, the part operate s in linear gain setting mode, loading each string resistor, r aw x and r wb x , with the value stored into the eeprom ( see table 17) . if the pin is pulled low, the part power s up in potentiometer mode . the indep pin and the d2 bit are connected internally to a logic or gate, if any o r both are 1 , the part cannot operate in potentiometer mode ( see table 18 ) . free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 25 of 32 ta ble 16. advance command operation truth table command number co ntrol bits [db15:db12] address bits [db11:db8] 1 data bits [db7:db0] 1 c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x x x nop: do nothing 1 0 0 0 1 0 a2 0 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to rdac 2 0 0 1 0 0 a2 0 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to input register 3 0 0 1 1 0 a2 a1 a0 x x x x x x d1 d0 read back contents d1 d0 d ata 0 0 input register 0 1 eeprom 1 0 control register 1 1 rdac 4 0 1 0 0 a3 a2 0 a0 x x x x x x x 1 linear rdac increment 5 0 1 0 0 a3 a2 0 a0 x x x x x x x 0 linear rdac decrement 6 0 1 0 1 a3 a2 0 a0 x x x x x x x 1 + 6 db rdac increment 7 0 1 0 1 a3 a2 0 a0 x x x x x x x 0 ? 6 db rdac decrement 8 0 1 1 0 a3 a2 0 a0 x x x x x x x x copy input reg ister to rdac (software l r dac) 9 0 1 1 1 0 a2 0 a0 x x x x x x x 1 copy rdac register to eeprom 10 0 1 1 1 0 a2 0 a0 x x x x x x x 0 copy eeprom into rdac 11 1 0 0 0 0 0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to eeprom 12 1 0 0 1 a3 a2 0 a0 1 0 0 0 0 0 0 d0 top s cale d0 = 0; normal mode d0 = 1; shutdown mode 13 1 0 0 1 a3 a2 0 a0 0 0 0 0 0 0 0 d0 bottom s cale d0 = 1; e nter d0 = 0; e xit 14 1 0 1 1 x x x x x x x x x x x x software reset 15 1 1 0 0 a3 a2 0 a0 0 0 0 0 0 0 0 d0 software shutdown d0 = 0; normal mode d0 = 1; device placed in shutdow n mode 16 1 1 0 1 x x x x x x x x x d2 d1 d0 copy serial register data to control register 1 x = dont care. free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 26 of 32 table 17 . address bits a3 a2 a1 a0 potentiometer mode linear gain setting mode stored channel memory input register rdac register input register rdac register 1 x 1 x 1 x 1 all c hannels all channels all channels all channels not applicable 0 0 0 0 rdac1 rdac1 r wb1 r wb1 rdac1/ r wb1 0 1 0 0 not applicable not applicable r aw1 r aw1 not applicable 0 0 0 1 rdac2 rdac2 r wb2 r wb2 r aw1 0 1 0 1 not applicable not applicable r aw2 r aw2 not applicable 0 0 1 0 not applicable not applicable not applicable not applicable rdac2/ r wb2 0 0 1 1 not applicable not applicable not applicable not applicable r aw2 1 x = dont care. table 18. control register bit description s b it name description d0 rdac register write protect 0 = wiper position frozen to value in eeprom memory 1 = allow s update of wiper position through digital interface (default) d1 eeprom program enable 0 = eeprom program disabled 1 = enable s devi ce for eeprom program (default) d2 lineal setting mode / potentiometer mode 0 = potentiometer mode (default) 1 = linea r gain setting mode free datasheet http:///
data sheet AD5122/ad5142 rev. 0 | page 27 of 32 rdac architecture to achieve optimum performance, analog devices, inc., has patented the rdac segmentation architecture for all the digital potentiometers. in particular, the AD5122 / ad5142 employ a t hree - stage segmentation approach , as shown in figure 41 . the AD5122 / ad5142 wiper switch is designed with the transmission gate cmos topology and with the gate voltage derived from v d d and v ss . 7-bit/8-bit address decoder r l w r l a r h r h r m r m b r m r m r h r h s ts s bs 10880-041 figur e 41 . AD5122 / ad5142 simplified rdac circuit top scale/bottom scale architecture in addition, the ad5 122/ ad5142 include new position s to reduce the resistance between terminals. these positions are called bottom scale and top scale. at bottom scale, the typical wiper resistance decreases from 130 ? to 6 0 ? (r ab = 100 k ? ). at top scale, the resistance between terminal a and terminal w is decreased by 1 lsb , and the total resistance is reduced to 60 ? (r ab = 100 k ? ) . programming the vari able resistor rheostat operation 8% resistor tolerance the AD5122 / ad5142 operate in rheostat mode when only two terminals are used as a variable resistor. the unused terminal can be floating , or it can be tied to terminal w , as shown in figure 42 . a w b a w b a w b 10880-042 figure 42 . rheostat mode configuration the nominal resistance between terminal a and terminal b, r ab , is 10 k or 10 0 k , and has 128 /256 tap points accessed by the wiper terminal. the 7 - bit /8 - bit data in the rdac latch is decoded to select one of the 128 /256 possible wiper settings. the general equations for determining the digitally programmed output resistance between t erminal w and t erminal b are AD5122 : w ab wb r r d d r + = 128 ) ( from 0x00 to 0x7f ( 1 ) ad5142 : w ab wb r r d d r + = 256 ) ( from 0x00 to 0x ff ( 2 ) where: d is the decimal equivalent of the binary code in the 7 - bit /8 - bit rdac register. r ab is the end - to - end resistance. r w is the wiper resistance . in potentiometer mode, similar to the mechanical potentiometer , the resistance between terminal w and terminal a also produces a digitally controlled complemen tary resistance, r wa . r wa also gives a maximum of 8% absolute resistance error. r wa starts at the maximum resistance value and decreases as the data loaded into the latch increases. the general equations for this operation are AD5122 : w ab aw r r d d r + ? = 128 128 ) ( from 0x00 to 0x 7 f ( 3 ) ad5142 : w ab aw r r d d r + ? = 256 256 ) ( from 0x00 to 0x f f ( 4 ) where: d is the decimal equivalent of the binary code in the 7 - bit /8 - bit rdac reg ister. r ab is the end - to - end resistance. r w is the wiper resistance . if the part is configured in linear gain setting mode, the resistance between terminal w and terminal a is directly proportional to the code loaded in the associate rdac register. the gen eral equations for this operation are AD5122 : w ab aw r r d d r + = 128 ) ( from 0x00 to 0x7f ( 5 ) ad5142 : w ab aw r r d d r + = 256 ) ( from 0x00 to 0xff ( 6 ) where: d is the decimal equivalent of the binary code in the 7 - bit /8 - bit rdac register. r ab is the end - to - end resistance. r w is the wiper resistance . free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 28 of 32 in the bottom scale condition or top scale condition, a finite total wiper resistance of 40 is present. regardless of which setting the part is operating in, limit the current between terminal a to terminal b, terminal w to terminal a, and terminal w to terminal b, to the maximum continuous current of 6 ma or to the pulse current specified in table 6 . otherwise , degradation or possible destruction of the internal switch contact can occur. programming the pote ntiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wi per - to - b and wiper - to - a that is proportional to the input voltage at a to b, as shown in figure 43 . w a b v a v out v b 10880-043 figure 43 . potentiometer mode configuration connecting terminal a to 5 v and t erminal b to ground pro duces an output voltage at the wiper w to terminal b ranging from 0 v to 5 v. the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminal a and terminal b is b ab aw a ab wb w v r d r v r d r d v + = ) ( ) ( ) ( ( 7 ) where : r wb ( d ) can be obtained from equation 1 and equation 2 . r aw ( d ) can be obtained from equation 3 and equation 4 . operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, r aw and r wb , and not the absolute values. therefore, the temperature drift reduces to 5 ppm/c. terminal voltage ope rating range the ad51 22/ ad5142 are designed with internal esd diodes for protection. these diodes also set the voltage boundary of the terminal operating voltages. positive signals present on terminal a, terminal b, or terminal w th at exceed v dd are clamped by the forward - biased diode. there is no polarity constraint between v a , v w , and v b , but they cannot be higher than v dd or lower than v ss . v dd a w b v ss 10880-044 figure 44 . maximum terminal voltages set by v dd and v ss power - up sequence because there are diodes to limit the voltage compliance at terminal a, terminal b, and terminal w ( see figure 44 ), it is important to power up v dd first before applying any voltage to terminal a, termina l b, and terminal w. otherwise, the diode is forward - biased such that v dd is powered unintentionally. the ideal power - up sequence is v ss , v dd , v logic , digital inputs, and v a , v b , and v w . the order of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v ss , v dd , and v logic . regardless of the power - up sequence and the ramp rates of the power supplies, once v logic is powered, the power - on preset activates , which restores eeprom values to the rdac registers. layout and pow er supply biasing it is always a good practice to use a compact, minimum lead length layout design. ensure that t he leads to the input are as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. it is also good practice to bypass the power supplies with quality capacitors. apply l ow equivalent series resistance (esr) 1 f to 10 f tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance and to filter low frequency ri pple. figure 45 illustrates the basic supply bypassing configuration for the AD5122 / ad5142 . v d d v l ogi c v d d + v ss c 1 0 . 1 f c 3 10 f + c 2 0 . 1 f c 4 10 f v s s v l ogi c + c 5 0 . 1 f c 6 10 f ad 512 2/ ad 514 2 g n d 108 80 - 0 45 figure 45 . power supply bypassing free datasheet http:///
data sheet AD5122/ ad5142 r ev. 0 | page 29 of 32 outline dimensions 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic a t or 0.50 0.40 0.30 sea ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. figure 46 . 16 - lead lead frame chip scale package [lfcsp_ w q ] 3 mm 3 mm body, very very thin quad (cp - 16 - 22 ) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 47 . 16 - lead thin shrink small outline package [tssop] (ru - 16 ) dimensions shown in millimeters free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 30 of 32 ordering guide model 1 , 2 r ab (k ) resolution interface temperature range package description package option branding AD5122 bcpz10 - rl7 10 128 spi ? 40c t o +125c 16- lead lfcsp_wq cp -16-22 dh8 AD5122 bcpz100 - rl7 100 128 spi ? 40c to +125c 16- lead lfcsp_wq cp -16-22 dh9 AD5122 b ru z10 10 128 spi ? 40c to +125c 16- lead tssop ru -16 AD5122 b ru z100 100 128 spi ? 40c to +125c 16- lead tssop ru -16 AD5122 b ru z10 - rl7 10 128 spi ? 40c to +125c 16- lead tssop ru -16 AD5122 b ru z10 0 - rl7 100 128 spi ? 40c to +125c 16- lead tssop ru -16 a d5142bcpz10 -r l 7 10 256 spi ? 40c to +125c 16- lead lfcsp_wq cp -16-22 dh5 ad5142 bcpz10 0 - rl7 100 256 spi ? 40c to +125c 16- lead lfcsp_ wq cp -16-22 dh6 ad5142 b ru z10 10 256 spi ? 40c to +125c 16- lead tssop ru -16 ad5142bruz100 100 256 spi ? 40c to +125c 16- lead tssop ru -16 ad5142 b ru z10 - rl7 10 256 spi ? 40c to +125c 16- lead tssop ru -16 ad5142bruz100 - rl7 100 256 spi ? 40c to +125c 1 6 - lead tssop ru -16 eval - ad5142dbz evaluation board 1 z = rohs compliant part . 2 the evaluation board is shipped with the 10 k? r ab resistor option; however, the board is compatible with all of the available resistor value options. free datasheet http:///
data sheet AD5122/ad5142 r ev. 0 | page 31 of 32 notes free datasheet http:///
AD5122/ad5142 data sheet rev. 0 | page 32 of 32 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective own ers. d10880 - 0- 10/12(0) free datasheet http:///

▲Up To Search▲

Price & Availability of AD5122

	To Download AD5122 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .